1. Field of the Invention
The present invention pertains in general to semiconductor devices, and more particularly to the manufacturing of a planar small dimensional memory cell array and its peripheral circuitry.
2. Description of Related Art
DRAM semiconductor devices have an advantage of a possible higher integration density as compared to other memory devices such as SRAM semiconductor devices, but DRAM semiconductor devices cannot maintain a decreasing stored charge, as required by scaling, due to leakage current from memory cells, internal noise, and soft errors caused by incident alpha particles. Therefore, the memory cells of such devices require constant refreshing in order to maintain data stored in the memory cells. Thus, power consumption is large even in stand-by mode.
Flash memory devices or EEPROM devices, on the other hand, have a merit in that there is no need to refresh the memory cells in order to maintain data stored in the memory cells. However, a primary drawback of flash memory devices is that it is difficult to improve its relative slow access time because it takes a relatively long time to program the memory cells. Moreover, a high voltage is necessary to program (write) or erase memory cells of flash memory devices. The high electric field applied during erase/write cycles degrades the SiO2 tunneling barrier to the floating gate over a predetermined number (typically about 105) of erase/write cycles and, as a result, limits the operational life of the memory device.
Thus, there is a need for a noble memory cell device that combines the advantages of DRAM and flash memory. In other words, there is a need for a semiconductor memory device having memory cells that allow scalable memory charge relative to cell density of the device with long-term retention, low voltage, high speed, and highly reliable operational characteristics. One such noble memory cell, which can be named as a Scalable Two-Transistor Memory cell, has been proposed by Nakazato et al. (refer to IEDM 97, pp. 179-182 and U.S. Pat. No. 5,952,692). Nakazato et al. referred to their device as a Planar Localized Electron Device Memory (PLEDM) cell. This memory cell has non-volatile, high-speed, very low-power dissipation, and high cell density characteristics. It also has an isolated memory node, which provides immunity against soft errors, a gain property, which provides a large S/N ratio. It is a quantum tunneling device working at room temperature with no hot carrier degradation effects, and can be fabricated by existing silicon processing technology.
FIG. 1 is a schematic diagram of a typical Scalable Two-Transistor Memory (here after referred to as STTM) cell. The STTM cell comprises a sensing transistor (1), which is also known as a read or an access transistor; and a programming transistor (2), which is also known as a write transistor. The sensing transistor is basically a conventional MOS transistor consisting of a floating gate (also acting as a storage node of the memory cell), a drain (acting as a sense line, S, corresponding to a bit line) and a source (acting as a ground line, G, at a ground or a certain potential). The programming transistor includes a multiple tunnel junction (MTJ) barrier structure, which is stacked on the storage node of the sensing transistor, with a control gate formed over the sidewalls of the barrier structure and the storage node, acting as a control gate line X (which is also known as the write line), and a source region which is electrically connected to the top region of the barrier structure acting as a data line Y. The storage node also acts as the drain region of the programming transistor. The programming transistor is basically a vertical channel transistor placed on top of a conventional floating gate MOS sensing transistor.
In the write mode, a data voltage is applied to the data line Y, and a write voltage (i.e., program voltage) is applied to the write (control gate) line X. Therefore, barrier height between the data line Y and the storage node is reduced, and tunneling current flows through the insulating layer. As a result, charges (electrons or holes) may be stored in the storage node. These stored charges change the threshold voltage of the sensing transistor. For example, in the event that the electrons are stored in the storage node and the sensing transistor is an NMOS transistor, the threshold voltage of the sensing transistor is increased towards the positive voltage. In a STTM cell, the write operation can be achieved with a low write voltage, as compared to the flash memory device. This is because in a STTM cell, the charge flow into the storage node is controlled by write (control gate) line X as well as the data line Y.
In order to read (sense) the data stored in a STTM cell, a read voltage is applied to the write (control gate) line X and an appropriate voltage is applied to the ground line G. Next, a sense amplifier (not shown) detects the current that flows through the sense line S. In this case, in the event that the threshold voltage of the sensing transistor is higher than the read voltage, the sense line current may not flow. If, however, the threshold voltage of the sensing transistor is lower than the read voltage, the sense line current may flow.
In the above STTM cell, the storage node is completely surrounded by insulating material (i.e., completely floated) unlike the storage node of a DRAM cell. Thus, in the event that the write voltage is much higher than the read voltage, there is no need to refresh the memory cells. Alternatively, the write (control gate) line can be separated into two write lines with the sensing transistor controlled by a first write line and the programming transistor controlled by a second write line. In this case, even though the write voltage approximates the read voltage, the programming transistor is not turned on during the read operation. Accordingly, it is not required to refresh the memory cell regardless of the difference between the write voltage and the read voltage.
As explained above, a unit STTM cell is operated by three control lines; the write (control gate) line, the bit line and the data line; whereas the unit DRAM cell is operated by only two control linesxe2x80x94the write line and the bit line. Thus, there continues to be a need for compact layout of the cell array region, data line extensions, and bit line extensions, in order to increase the integration density of STTM devices. Also, there continues to be a need for noble column addressing schemes to the bit lines and data lines in a limited cell pitch.
The present invention is directed to a processing sequence required for making a STTM cell array with a unit cell area as low as 4F2, where F is a minimum feature size, that corresponds to the width of the data line or write line and also the spacing between the data lines or the write lines. The processing sequence and conditions are designed to offer wide flexibility in terms of material choices and layer thickness at different regions of the STTM cell with surface planarity maintained at several stages of the manufacturing sequence. The processing sequence is designed for making both memory cell and peripheral devices simultaneously, to save the total processing time.
According to a feature of a preferred embodiment of the present invention, there is provided a self-aligned processing sequence for making a Scalable Two-Transistor Memory (STTM) cell array with a minimum unit cell area of 4F2, where F represents the minimum feature size and also the width (and also the spacing) of the data lines or the write (control gate) lines. An STTM cell consists of a sensing (bottom) transistor and a programming (top) transistor. The programming (top) transistor has a multiple tunnel junction (MTJ) barrier structure on the floating gate of a sensing MOS transistor. According to a preferred embodiment of the present invention, the method of the present invention provides processing sequence and processing conditions for fabricating a memory cell array that are designed to offer a wide flexibility in terms of material choices and layer thickness at different regions of the STTM cell with surface planarity maintained at several stages of the manufacturing sequence in order to improve the device yield.
In the present invention, the entire or part of the large band gap insulator layer of the MTJ barrier structure may be formed using chemical vapor deposition (CVD) technique which allows a wide choice of materials such as silicon nitride, silicon oxide, silicon oxy-nitride, metal oxides, metal nitrides, etc. as possible insulator layer materials. The double sidewall gate insulating layer of the programming (top) transistor may contain multi-layered dielectric materials with layers deposited entirely by CVD or a combination of layers formed by thermal treatment and CVD.
As mentioned above, a feature of an embodiment of the present invention is to provide a smooth surface topology (planarity) at several stages of the processing sequence in order to improve the device""s processing yield. In a preferred embodiment, additional metal, metal silicide or polycide layers are formed on top of the silicon layers to minimize the resistance of sense lines (bit lines) and data lines.
In the present invention, the processing of memory cell devices is made compatible with periphery devices so that the devices in both areas can be made simultaneously, thereby decreasing the total number of processing steps and, hence, lowering the manufacturing cost. Forming of isolation trenches around the devices, filling of the trenches with oxide insulator, forming of the source/drain and the gate regions of the peripheral devices are done simultaneously with the corresponding regions of the memory cell devices.
These and other features of the present invention are realized by the present invention wherein according to a preferred embodiment, there is provided a method of manufacturing a scalable two-transistor memory (STTM) cell array having three control lines including bit lines, data lines and word lines, each memory cell having a bottom transistor and a top transistor in a stacked configuration, comprising the steps of:
providing a substrate having an x-axis and a y-axis;
depositing a first gate dielectric layer on the substrate;
depositing a first conductive layer on the first gate dielectric layer to form a storage node;
depositing alternating layers of a low band gap semiconductor layer and a large band gap insulator layer to form a multiple tunnel junction barrier on the storage node layer;
depositing a second conductive layer to form a source layer of the top transistor;
etching the second conductive layer, multiple tunnel junction layer, the first conductive layer and the first gate dielectric layer into the substrate to form a plurality of island-type trench isolation regions using a photolithographic process;
depositing a first insulating layer over the substrate to fill the trench regions;
depositing a third conductive layer over the first insulating layer to form data lines;
etching the third conductive layer, the second conductive layer, multiple tunnel junction layer, the first conductive layer and the first gate dielectric layer until the substrate surface is exposed, to form grooves in a direction parallel with the y-axis in between the island-type filled trench isolation regions;
implanting impurities in the exposed substrate to form the source/drain extension regions of the bottom transistor in the grooves formed in a direction parallel with the y-axis using a photolithographic process;
forming bit lines in the grooves formed in a direction parallel with the y-axis;
depositing a second insulating layer over the cell array and etched grooves in a direction parallel with the y-axis;
forming a photoresist pattern defining control gate lines over the second insulating layer;
performing an etching process to etch away the second insulating layer between and on top of adjacent memory cells in a direction parallel with the x-axis;
removing the photoresist pattern;
depositing second gate dielectric layers on the sidewalls of the multiple tunnel junction barrier structure;
depositing fourth conductive layer over the entire surface of the array; and
forming the word lines by chemical mechanical polishing (CMP) or etching of the fourth conductive layer.
According to other features of the present invention, the substrate material is selected from the group consisting of silicon, silicon germanium, silicon germanium on silicon, silicon germanium carbide on silicon, and silicon on insulator (SOI). The first gate dielectric layer is a silicon oxide layer of thickness between about 15-100 angstroms. The first conductive layer is a doped semiconductor storage node layer having a thickness of up to 5,000 angstroms. The second conductive layer forming the source layer of the top transistor is also a doped semiconductor layer having a thickness of up to 5000 angstroms. Both the storage node and the source layer of the top transistor are made of a material selected from the group consisting of silicon, germanium, silicon germanium, and silicon germanium carbide. The multiple tunnel junction (MTJ) barrier on the storage node is made of 2-20 alternating layers of low band gap ( less than 2 eV) semiconductor layers of thickness up to 1,000 angstroms and large band gap ( less than 10 eV) insulator layers of thickness up to 100 angstroms. Material used for the low band gap semiconductor layers forming the MTJ barrier is selected from the group consisting of either undoped or doped silicon, germanium, silicon germanium, and silicon germanium carbide. The low band gap semiconductor layers forming the MTJ barrier are deposited on the storage node layer under a temperature range where the as-deposited semiconductor layer is in an amorphous phase or in a polycrystalline phase. Typical temperature range used to deposit low band gap semiconductor layers of the MTJ barrier is 300-900 degrees centigrade. Material used for the large band gap insulator layers forming the MTJ barrier is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, metal oxides (like HfOx, ZrOx, Al2O3) and metal nitrides (like AIN).
According to another feature of an embodiment of the present invention, a chemical mechanical polishing (CMP) stopping layer is deposited on the second conductive layer, which is the source layer of the programming (top) transistor. Typical CMP stopping layer material is SiN.
According to another feature of an embodiment of the present invention in order to obtain plurality of trench isolation regions between the memory cells in the y-axis direction, the CMP stopping layer is etched first to form a CMP stopping layer pattern. The CMP stopping layer pattern acts as an etch mask while etching the second conductive layer, the MTJ layer, the first conductive layer, the first gate dielectric layer and the substrate to form a plurality of trench regions. The trench regions are then filled with the first insulating layer, which is a material such as silicon oxide. The substrate, with the MTJ layer and other active layers on top of it, is then subjected to CMP to achieve a smooth surface across the substrate. The CMP stopping layer is then removed and the third conductive layer is formed over the first insulating layer and the second conductive layer. The third conductive layer material is selected from the group consisting of a heavily doped polysilicon, polycide and metals.
According to another feature of an embodiment of the present invention an optional cleaning process may be performed as needed to remove a native oxide layer on the second conductive (doped semiconductor) layer pattern before depositing the third conductive layer.
According to another feature of an embodiment of the present invention, a capping layer is deposited over the third conductive layer. The material used for the capping layer typically is SiN. By using a photolithographic process the capping layer and then the third conductive layer, the second conductive layer, the MTJ layer, the first conductive layer, and the first gate dielectric layer are sequentially etched until the substrate surface is exposed, to form grooves in a direction parallel with y-axis in between the island type filled trench isolation regions. The second conductive layer and the layers under it are dry etched using the capping layer as an etch mask. This results in a self-aligned etching process.
According to another feature of an embodiment of the present invention, the bottom layer of the top transistor (or second) gate dielectric layers is formed before implanting impurities in the exposed substrate to form the source/drain extension regions of the bottom transistor. The bottom layer of the second gate dielectric layers is formed by a thermal oxide or a multiple insulator combination including the thermal oxide. Formation of the bottom layer of the second gate dielectric layers using a thermal oxidation step cures damage caused by dry etching to the MTJ barrier layer sidewall and to the substrate surface between the data lines.
According to another feature of an embodiment of the present invention, a sidewall spacer is formed on the sidewall surface of the memory cell in the grooves formed in a direction parallel with y-axis after the source/drain extension regions of the bottom transistor are formed. The sidewall spacer is formed of an oxide layer or a nitride layer. After the sidewall spacers are formed, the substrate is subjected to a heavy dose of ion implantation to form a heavily doped section within the source/drain extension regions of the bottom transistor. These heavily doped sections within the source/drain extension regions may create a metallization effect forming the bit lines. In an alternate way, to form bit lines, a heavily doped polysilicon or a salicidation or a polycide or a metal deposition step is performed on the heavily doped sections within the source/drain extension regions of the bottom transistor. The sidewall spacers are removed after forming the bit lines. According to another feature of an embodiment of the present invention, the sidewall spacers are removed before depositing the top layer of the second gate dielectric layers on the sidewalls of the MTJ barrier structure.
According to yet another feature of an embodiment of the present invention, a conformal etch stop layer is formed on the entire surface of the memory cell array after forming the bit lines, but before depositing the second insulating layer over the cell array. The material used for the conformal etch stop layer is SiON or SiN. Material used to form the second insulating layer on the conformal etch stop layer to fill the etched grooves in a direction parallel with the y-axis is typically a CVD oxide. After depositing the second insulating layer a CMP process is performed in order to planarize the entire memory cell array surface. After etching the second insulating layer formed in the grooves in between the memory cells and on top of the memory cells, in a direction parallel with the x-axis, the conformal etch stop layer between adjacent memory cells in a direction parallel with the x-axis is etched until the portions of the bit lines underneath are exposed. The etching processes used in this invention are either dry and/or wet etching. A CVD oxide or a CVD nitride layer is deposited over the entire surface of the array to cover the exposed bit line regions and to form a top layer of the second gate dielectric layers on the sidewalls of the top transistors of the memory cells.
According to another feature of an embodiment of the present invention, the top transistor (or second gate) dielectric layers are multi-layered insulators. These multi-layered insulators are a combination of thermally grown and deposited layers. The multi-layered insulators are selected from a group consisting of SiO, SiN, SiON, metal oxides and metal nitrides. After forming the second gate dielectric layers, the word lines are formed on them by depositing a fourth conductive layer which is a metal, polysilicon/metal or polysilicon/silicide damascene process. Typical material systems used to form word lines are Ti/W or TiN/silicide. After depositing the fourth conductive layer a CMP process is performed to planarize the entire surface of the memory array and to remove unwanted fourth conductive layer material until the word lines are formed.
According to another feature of an embodiment of the present invention, there is provided a method of manufacturing peripheral circuitry CMOS devices of a scalable two-transistor memory having a memory device array according to the present invention, comprising the steps of:
forming a gate dielectric layer, a first conductive layer, alternating layers of a multiple tunnel junction (MTJ) barrier, a second conductive layer, and a CMP stopping layer at the same time these layers are formed for the memory device array;
selectively removing the CMP stopping layer, the second conductive layer and the MTJ barrier layers all on top of the CMOS device areas and leaving the first conductive layer and the oxide layer underneath as part of the peripheral CMOS device gate structure;
forming source/drain regions of the peripheral CMOS devices; and
forming a conductive layer on top of the peripheral CMOS device gate structure at the same time data lines of the memory cell array are formed.
The source/drain regions of the peripheral CMOS devices may be formed at the same time the corresponding regions of the sensing (bottom) transistors of the memory cell arrays are formed. Additionally, contacts to the source/drain regions of the peripheral CMOS device may also be formed at the same time contacts are made to the sensing (bottom) transistors of the memory cell array. Metals, highly doped polysilicon, polycide or salicide may be used to form contacts to the source/drain regions of the periphery devices. Material for the conductive gate layer of the periphery CMOS devices is selected from the group consisting of metals, doped poly-silicon, polysilicon/metal and polysilicon/silicide.